1. Field of the Invention
The disclosure relates generally to verification for HDL designs, and, more particularly, verification for HDL designs which contain System Verilog “interface” constructs.
2. Description of the Related Art
In recent years, the developing process of integrated circuits such as super larger scale integrated circuits (LSIs) generally utilizes computer assisted design (CAD). According to such a developing process based on CAD, abstract circuit data, which corresponds to functions of an integrated circuit to be developed, is defined by using a so-called hardware description language (HDL), and the defined circuit SIN3 is used to form a concrete circuit structure to be mounted on a chip.
In general, a design engineer enters the description of a digital circuit in a textual format in HDL, like VHDL, Verilog, SystemC, SystemVerilog and others. SystemVerilog is an extension to Verilog 2.0, combining Hardware Description Language and Hardware Verification Language. SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow.